DocumentCode :
2807567
Title :
Enhancing component level reliability of Pb-free flip chip package of Cu/low-K devices using FEM-based sensitivity analysis
Author :
Chang, Kuo-Chin ; Lee, Chang-Chun ; Pu, Han-Ping ; Lii, Mirng-Ji
Author_Institution :
Taiwan Semicond. Manuf. Co. Ltd., Hsinchu
fYear :
2007
fDate :
1-3 Oct. 2007
Firstpage :
75
Lastpage :
78
Abstract :
As the Cu/low-k interconnects integrated into the next-generation IC chip, particularly for devices below 90 nm, to meet the requirements of reducing RC time delay and low power consumption, how to establish a feasible and robust solution of packaging technology regarding to the structural design as well as the material selection of packaging components has become more important to fulfill the fast progress of semiconductor industry. Although eutectic Sn-Pb solder is the mainstream interconnections between components at present, due to environmental issues with the Pb ingredient of the Sn-Pb solder, the electronic industry tends to utilize Pb-free solder. At this time, the nature of low-k materials and the replacement of Pb-free solder greatly increase the complication in ensuring the enhancement of packaging level reliability. The foregoing urgent issue needs to be quickly resolved when developing various advanced packages. To this end, the prediction model of fatigue life for Pb-free solder joint combined the virtual design of experiment (DOE) with factorial analysis is used to obtain the sensitivity information of selecting geometry/material parameter in the proposed low-k flip-chip (FC) package. Moreover, a three- dimensional (3D) nonlinear strip finite element (FE) model combined with the two levels of specified boundary condition (SBC) of global-local technique is adopted to shorten the time of numerical calculation as well as to possess an accurate solution. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Moreover, the sensitivity of analysis indicates the type of underfill material has a significant effect on the Pb-free solder joint reliability. Furthermore, a suitable combination of concerned designed factors is suggested in this research to enhance the reliability of Cu/low-k FC packaging with Pb-free solder joints.
Keywords :
chip scale packaging; copper; finite element analysis; flip-chip devices; integrated circuit interconnections; integrated circuit reliability; low-k dielectric thin films; sensitivity analysis; 3D nonlinear strip finite element model; Cu; Cu/low-k interconnects; FEM-based sensitivity analysis; RC time delay; component packaging level reliability; environmental issues; global-local technique; lead-free flip chip packaging technology; lead-free solder joint reliability; semiconductor industry; specified boundary condition; thermal cycling; underfill material; Electronics industry; Electronics packaging; Flip chip; Integrated circuit packaging; Joining materials; Materials reliability; Semiconductor device packaging; Semiconductor materials; Sensitivity analysis; Soldering; Cu/low-k interconnects; Flip-chip; Global-local finite element method (FEM); Pb-free solder bump;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology, 2007. IMPACT 2007. International
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-1636-3
Electronic_ISBN :
978-1-4244-1637-0
Type :
conf
DOI :
10.1109/IMPACT.2007.4433571
Filename :
4433571
Link To Document :
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