DocumentCode :
2807770
Title :
On-chip global signaling by wave pipelining
Author :
Hashimoto, Masanon ; Tsuchiya, Akin ; Onodera, Hidetoshi
Author_Institution :
Dept. of ISE, Osaka Univ., Japan
fYear :
2004
fDate :
25-27 Oct. 2004
Firstpage :
311
Lastpage :
314
Abstract :
This work discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.
Keywords :
CMOS logic circuits; integrated circuit interconnections; integrated circuit modelling; invertors; pipeline processing; CMOS static repeater insertion; conventional repeater insertion signaling; on-chip global signaling performance; on-chip transmission lines; wave pipelining; Clocks; Delay; Frequency; Integrated circuit interconnections; Pipeline processing; Power transmission lines; Repeaters; Throughput; Transmission line theory; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2004. IEEE 13th Topical Meeting on
Print_ISBN :
0-7803-8667-1
Type :
conf
DOI :
10.1109/EPEP.2004.1407619
Filename :
1407619
Link To Document :
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