The development of chip embedded for IC substrate

With the continued demand for microelectronic system with multi-function, high speed and high density, package technology with embedded chips integrated in substrate could provide the shortest interconnection between the die and substrate and may reduce the inductance and noise interference. As more and more increasing of the functionality in I.C. development, the number of passive components accompanied with active device is extremely increasing. Due to the high speed of the microelectronic devices, capacitors need to be as close to the I.C. as possible to avoid the parasitic effects. However, the embedded technology may face some problems such as the mechanical-thermal stresses and the warpage of the package so that the poor interconnects were achieved. In this paper, we demonstrate the methodology of embedded technology in which the ceramic capacitor chips were placed in the core of the substrate. The package solution enables the capacitors disposing in the substrate to minimize the circuit length, therefore the inductance and the noise interference could be reduced. Since the selected passive components were embedded inside the substrate, more design space could be used for high density and high performance requirements. The embedded samples in this development can pass to substrate-level and package-level reliability test. The fabrication data and reliability data were demonstrated in this manuscript.