Capacitance Characterization of Interconnection Crossing and Patch in Multilevel Package

Author

Hassaïne, N. ; Villeneuve, L. ; Shen, Y.

Author_Institution

Harris Corp., Dollard-Des-Ormeaux

fYear

2007

fDate

22-26 April 2007

Firstpage

95

Lastpage

98

Abstract

This paper is devoted to the capacitance computing and characterization of interconnection crossing and patch used in multilevel package. The [C] matrix calculation is performed with scalar potential given in its integral form. Analytical formulas easy to use in CAD systems have been derived from numerical results using least square method. A good agreement has been achieved between simulations and experimental results.

Keywords

capacitance; circuit CAD; integrated circuit interconnections; integrated circuit packaging; least squares approximations; matrix algebra; method of moments; CAD systems; [C] matrix calculation; capacitance characterization; interconnection crossing characterization; least square method; multilevel package; scalar potential; Circuit simulation; Delay effects; Equations; Geometry; Integrated circuit interconnections; Least squares methods; Microwave communication; Moment methods; Packaging; Parasitic capacitance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2007. CCECE 2007. Canadian Conference on

Conference_Location

Vancouver, BC

ISSN

0840-7789

Print_ISBN

1-4244-1020-7

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2007.31

Filename

4232690