Fault tolerant design of neuro-processors using weight limitation and ternary output

This paper presents a fault tolerant design of hardware-type neural networks for real time control usage combining the following two methods; (1) a method to reduce the effect of a fault by weight limitation of synapses and (2) a method to reduce the effect of a fault by setting the output of the faulty neuron to the middle level of the ternary logic. Fault simulation is carried out on a numeric pattern recognition system that is implemented using a 3-layered feed-forward neural network. Fault generation is assumed to occur on a neuron rather than an interconnection line. It is demonstrated that a fault tolerant design of neural networks to cover all of the neurons included in the input layer, intermediate layer and output layer can be carried out by combining the weight limitation and the ternary output.