DocumentCode
2809702
Title
Detection of critical hazards in digital MOS VLSI circuits by switch-level timing simulation
Author
Sass, D. ; Warmers, H. ; Horneber, E., II
Author_Institution
Inst. fuer Netzwerktheorie & Schaltungstech., Tech. Univ. Braunschweig, Germany
fYear
1990
fDate
12-14 Aug 1990
Firstpage
584
Abstract
The approach presented was implemented in the switch-level simulator BRASIL. All hazards occurring in a digital MOS circuit are reliably detected and the worst-case approximated by simulation with BRASIL. Hence, hazard propagation which can lead to a malfunction of the ensuing gates can easily be observed. In spite of handling signal waveforms, run time reduction of BRASIL is two to three orders of magnitude compared to SPICE2
Keywords
MOS integrated circuits; VLSI; digital integrated circuits; digital simulation; hazards and race conditions; BRASIL; critical hazards; digital MOS VLSI circuits; hazard propagation; run time reduction; signal waveforms; switch-level simulator; switch-level timing simulation; Circuit faults; Circuit simulation; Hazards; Logic circuits; Logic design; Parasitic capacitance; Switching circuits; Timing; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location
Calgary, Alta.
Print_ISBN
0-7803-0081-5
Type
conf
DOI
10.1109/MWSCAS.1990.140786
Filename
140786
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