Title :
Efficient test generation for CMOS circuits
Author :
Radhakrishnan, Damu ; Lai, Congmin
Author_Institution :
NETCH Corp., Hicksville, NY, USA
Abstract :
A new concept, path testing, is introduced. This approach leads to the simultaneous testing of a set of MOS transistors in a path of a CMOS circuit instead of individual ones. Using this concept, the authors generate a Karnaugh map procedure to identify a minimal robust test set for a direct CMOS complementary gate. The test set derived is implementation independent, and it can be used for detecting both single and multiple faults
Keywords :
CMOS integrated circuits; digital integrated circuits; integrated circuit testing; logic testing; CMOS circuits; Karnaugh map procedure; direct CMOS complementary gate; implementation independent; minimal robust test set; multiple fault detection; path testing; simultaneous testing; single fault detection; test generation; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; MOS devices; MOSFETs; Robustness; Semiconductor device modeling; Sequential circuits; Switches;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140787
