DocumentCode
2810114
Title
Array noise analysis for high-density dynamic RAM design
Author
Yuan, J.S. ; Liou, J.J.
Author_Institution
Univ. of Central Florida, Orlando, FL, USA
fYear
1990
fDate
12-14 Aug 1990
Firstpage
649
Abstract
The analytical modeling of the bit line noise analysis for different DRAM architectures has been developed. The analytical expressions provide insight into the charge redistribution when the word lines turn on. The topology for array noise extraction in SPICE circuit simulation is presented. The SPICE simulations show good agreement with analytical results
Keywords
DRAM chips; VLSI; circuit analysis computing; crosstalk; electron device noise; DRAM architectures; SPICE circuit simulation; analytical expressions; analytical modeling; array noise extraction; bit line noise analysis; capacitive coupling; charge redistribution; high-density dynamic RAM; scaling; topology; word line turn on; Analytical models; Capacitance; Circuit noise; DRAM chips; Degradation; Equations; Noise level; Random access memory; SPICE; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location
Calgary, Alta.
Print_ISBN
0-7803-0081-5
Type
conf
DOI
10.1109/MWSCAS.1990.140802
Filename
140802
Link To Document