• DocumentCode
    2810138
  • Title

    A crosstalk tolerant latch circuit design

  • Author

    Rubio, A. ; Pons, J. ; Anglada, R.

  • Author_Institution
    Dept. of Phys., Univ. of Balearic Islands, Palma, Spain
  • fYear
    1990
  • fDate
    12-14 Aug 1990
  • Firstpage
    653
  • Abstract
    A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range of or even higher than ±Vdd, becoming under specific conditions a dynamic latch preserving the system from the propagation of unknown quality information. The circuit and the design rules presented are oriented to VLSI circuits design in which crosstalk perturbations may be foreseen
  • Keywords
    CMOS integrated circuits; VLSI; crosstalk; digital integrated circuits; flip-flops; CMOS; D-latch sequential circuit; VLSI; clock signal noise; common mode noise; complementary lines; crosstalk perturbations; crosstalk tolerant latch circuit design; design rules; differential mode noise; dynamic latch; high amplitude noise; high tolerance to noise; noise immunity; CMOS logic circuits; Circuit noise; Circuit synthesis; Clocks; Crosstalk; Distributed parameter circuits; Interference; Latches; Sequential circuits; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
  • Conference_Location
    Calgary, Alta.
  • Print_ISBN
    0-7803-0081-5
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1990.140803
  • Filename
    140803
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2810138