A 2.5 Gb/s, Low Power Clock and Data Recovery Circuit

This paper presents an all-digital clock and data recovery circuit with the data bit rate of 2 to 5Gb/s. With the eye-tracking technique instead of the traditional data edge tracking method, the jitter tolerance is increased by keeping the sampling clock away from the jitter distribution region confirmed by Matlab simulation. A bang-bang PD with a phase distance of 1/4 UI is chosen, and a jitter tolerance of 0.75UI is achieved. A CMOS circuit was implemented in CMOS 90 nm technology with low complexity. The circuit consumes a power of 9 mW at 2.5 Gbps at a 1.2 v supply.