Title :
A family of CMOS linear resistors
Author :
Chan, P.K. ; Wilson, G.
Author_Institution :
Sch. of Electron., Commun. & Electr. Eng., Plymouth Univ., UK
Abstract :
It is known that quadratic distortion in the drain current for MOSFET devices operating in the so-called linear region can be suppressed either by applying suitably scaled terminal signals to the gate (with the bulk node hel at an appropriate DC bias level; usually V DD or VSS) or by driving both the gate and bulk nodes with unscaled signals. This contribution describes a range of CMOS resistor structures based on building blocks consisting of buffered linear-mode transistors in which the gates and bulks are simultaneously modulated
Keywords :
CMOS integrated circuits; insulated gate field effect transistors; linear integrated circuits; CMOS linear resistors; MOSFET devices; buffered linear-mode transistors; bulk nodes; drain current; gate nodes; quadratic distortion; terminal signals; unscaled signals;
Conference_Titel :
Linear Analogue Circuits and Systems, IEE Colloquium on
Conference_Location :
Oxford
