A family of CMOS linear resistors

It is known that quadratic distortion in the drain current for MOSFET devices operating in the so-called linear region can be suppressed either by applying suitably scaled terminal signals to the gate (with the bulk node hel at an appropriate DC bias level; usually V _DD or V_SS) or by driving both the gate and bulk nodes with unscaled signals. This contribution describes a range of CMOS resistor structures based on building blocks consisting of buffered linear-mode transistors in which the gates and bulks are simultaneously modulated