Title :
A physical SPICE-compatible dual-gate JFET model
Author_Institution :
Dept. of Electr. Eng., Portland State Univ., OR
Abstract :
A physical dual-gate JFET model is presented. The model is based on the physical three-half power current-voltage relationship. This model has the capability of independent biasing of top-gate and bottom-gate. Short channel velocity-saturation and an improved channel-length modulation model are also included. The model has been developed as a subroutine extension in SPICE. Self-consistent parameter extraction routines, based on an exact operational definition of each model parameter, have been developed in conjunction with the model. Unique extraction algorithms are developed for each model form. Only after consistent extraction routines are developed for the model within a circuit simulator are they applied to the physical device. This provides an exact operational definition for each model parameter
Keywords :
electronic engineering computing; junction gate field effect transistors; semiconductor device models; SPICE compatibility; bottom gate biasing; channel-length modulation model; dual-gate JFET model; parameter extraction routines; physical three-half power current-voltage relationship; short channel velocity saturation; top gate biasing; Algorithms; Circuit simulation; Equations; Intrusion detection; JFET integrated circuits; Marine vehicles; Parameter extraction; Power engineering and energy; SPICE; Voltage;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140819
