DocumentCode
2810624
Title
Clock-feedthrough compensated digital-to-analog converters
Author
Matsumoto, Hiroki ; Tang, Zheng ; Ishizuka, Okihiko
Author_Institution
Dept. of Electron. Eng., Miyazaki Univ., Japan
fYear
1990
fDate
12-14 Aug 1990
Firstpage
744
Abstract
Switched-capacitor (SC) digital-to-analog (D/A) converters which are insensitive to clock-feedthrough charge caused by MOS analog switches, offset- and gain-error of unity gain buffers (UGB) are presented. Because their configurations are based on UGB, the conversion rate is estimated to 90 Mb/s. Resolution of the proposed converter is limited by top plate parasitic capacitance and can be reached up to 9 bit
Keywords
CMOS integrated circuits; compensation; digital-analogue conversion; switched capacitor networks; 90 Mbit/s; CMOS process; MOS analog switches; clock feedthrough compensation; conversion rate; digital-to-analog converters; gain-error; offset error; resolution; switched capacitor D/A converters; top plate parasitic capacitance; unity gain buffers; CMOS integrated circuits; CMOS process; Clocks; Digital-analog conversion; Equations; MOS capacitors; Signal processing algorithms; Switches; Switching converters; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location
Calgary, Alta.
Print_ISBN
0-7803-0081-5
Type
conf
DOI
10.1109/MWSCAS.1990.140827
Filename
140827
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