Title :
Table of contents
Abstract :
The following topics are dealt with: 3D chip testing; automatic test equipment; board-level testing; built-in self-test; defect oriented testing; design for testability; diagnosis and debug; embedded core testing; hardware security; high-speed interface testing; interconnect characterization; memory testing; mixed-signal/analog testing; nanometer technology testing; on-line and field testing; performance/delay testing; microprocessor testing; power issues in testing; system-level test economics; test synthesis; test resource partitioning; test related standards; verification and validation; wafer testing and yield optimization.
Keywords :
automatic test equipment; built-in self test; design for testability; embedded systems; integrated circuit testing; interconnections; microprocessor chips; program debugging; program diagnostics; 3D chip testing; automatic test equipment; board-level testing; built-in self-test; defect oriented testing; delay testing; design for testability; diagnosis and debug; embedded core testing; field testing; hardware security; high-speed interface testing; interconnect characterization; memory testing; microprocessor testing; mixed-signal/analog testing; nanometer technology testing; online testing; performance testing; power issues in testing; system-level test economics; test related standards; test resource partitioning; test synthesis; verification and validation; wafer testing; yield optimization;
Conference_Titel :
Test Conference (ITC), 2012 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4673-1594-4
DOI :
10.1109/TEST.2012.6401523
