DocumentCode :
2810996
Title :
Adaptive test selection for post-silicon timing validation: A data mining approach
Author :
Ming Gao ; Lisherness, P. ; Kwang-Ting Cheng
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of California, Santa Barbara, Santa Barbara, CA, USA
fYear :
2012
fDate :
5-8 Nov. 2012
Firstpage :
1
Lastpage :
7
Abstract :
Test failure data produced during post-silicon validation contain accurate design- and process-specific information about the DUD (design-under-debug). Prior research efforts and industry practice focused on feeding this information back to the design flow via bug root-cause analysis. However, the value of this silicon data for helping further improvement of the post-silicon validation process has been largely overlooked. In this paper, we propose an adaptive test selection method to progressively tune the validation plan using knowledge automatically mined from the bug sightings during post-silicon validation. Experimental results demonstrate that the proposed fault-model-free data mining approach can prioritize those tests capable of uncovering more silicon timing errors, resulting in significant reduction of validation time and effort.
Keywords :
data mining; electronic engineering computing; elemental semiconductors; integrated circuit modelling; integrated circuit testing; silicon; Si; adaptive test selection; bug root-cause analysis; design-under-debug; fault-model-free data mining; post-silicon timing validation; process-specific information; test failure data; Accuracy; Computer bugs; Data mining; Delay; Silicon; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference (ITC), 2012 IEEE International
Conference_Location :
Anaheim, CA
ISSN :
1089-3539
Print_ISBN :
978-1-4673-1594-4
Type :
conf
DOI :
10.1109/TEST.2012.6401540
Filename :
6401540
Link To Document :
بازگشت