Hierarchical buffer management for ATM switches

We present the design of a buffer management scheme for an ATM switch with a shared buffer, when the buffer is logically organized into multiple buffer levels. Conventional schemes statically allocate buffer space in each buffer level through the use of buffer thresholds. Although very simple, these static thresholds are often determined using heuristics and cannot adapt to changing traffic conditions. The latter could result in unnecessary cells dropped which leads to poor switch performance. Our scheme adapts to changing load conditions and dynamically allocates buffer space in all buffer levels in a recursive fashion. Simulation results, which compare performance of our scheme with the fair buffer allocation (FBA) scheme, are presented