A microelectronic core for a programmable digital hearing aid

Author

Hidalgo, J.A. ; Tejero, J.C. ; Daza, A. ; Oballe, O. ; Gago, A.

Author_Institution

Dept. de Electron., ETSI Ind., Malaga, Spain

fYear

1997

fDate

19-22, Oct 1997

Abstract

We introduce a core for a digital hearing aid that compensates the signal spoken in sensorineural impaired listeners with object of improving their intelligibility. The technique implemented is based on a digital analysis/synthesis of speech: we divided the input signal into short time blocks then we make a multiband analysis, non-linear amplification and synthesis based in a sinusoidal model of the voice, according to the subject´s dynamic range in each band. The system works in real time and has been implemented with only one ASIC in 1μ ES2 technology including 3 RAM memories with a capacity of 2432 bits and one 16×16 multiplier. The size of the die is 30.59 mm²

Keywords

application specific integrated circuits; compensation; digital signal processing chips; hearing aids; speech intelligibility; speech processing; speech synthesis; 1μ ES2 technology; 2432 bit; ASIC; RAM memories; die size; digital analysis; digital synthesis; dynamic range; input signal; intelligibility; microelectronic core; multiband analysis; multiplier; nonlinear amplification; programmable digital hearing aid; sensorineural impaired listeners; short time blocks; sinusoidal model; speech; voice; Application specific integrated circuits; Auditory system; Dynamic range; Microelectronics; Random access memory; Real time systems; Signal analysis; Signal synthesis; Speech analysis; Speech synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Applications of Signal Processing to Audio and Acoustics, 1997. 1997 IEEE ASSP Workshop on

Conference_Location

New Paltz, NY

Print_ISBN

0-7803-3908-8

Type

conf

DOI

10.1109/ASPAA.1997.625577

Filename

625577