Optimization of a high-voltage MOSFET in ultra-thin 14nm FDSOI technology

We investigate a promising high-voltage MOSFET (HVMOS) fabricated in the leading edge 14nm Fully-Depleted Silicon-On-Insulator technology (FDSOI). We focus on a variant of the Extended-Drain MOSFET (EDMOS) on SOI which features Ultra-Thin Body and Buried oxide (UTBB) and Dual Ground Plane configuration (DGP). The independent biasing of two different ground planes located under the device enables, without film doping, to control separately the electrostatic properties of the channel and the drift regions. Electrical characteristics such as breakdown voltage and specific on-resistance are explored for different layout geometries and backgate voltage. Encouraging results of the DGP EDMOS in 14nm FDSOI are presented for 5V power management.