Title :
A memory yield improvement scheme combining built-in self-repair and error correction codes
Author :
Tze-Hsin Wu ; Po-Yuan Chen ; Mincent Lee ; Bin-Yen Lin ; Cheng-Wen Wu ; Chen-Hung Tien ; Hung-Chih Lin ; Hao Chen ; Ching-Nen Peng ; Min-Jer Wang
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Error correction code (ECC) and built-in self-repair (BISR) schemes have been wildly used for improving the yield and reliability of memories. Many built-in redundancy-analysis (BIRA) algorithms and ECC schemes have been reported before. However, most of them focus on either BIRA algorithms or ECC schemes. In this paper, we propose an ECC-Enhanced Memory Repair (EEMR) scheme for yield improvement. Many modern memories are equipped with ECC in addition to BISR. We evaluate the back-end flow that combines both ECC and BIRA to determine whether yield can be improved by proper sequencing of the two steps. We also collect and identify important failure patterns and their distributions from over 100,000 sample memory instances, which are used to enhance the EEMR scheme that incorporates ECC. As ECC is failure pattern sensitive, careful evaluation from realistic failure bitmaps is necessary. We also verify the feasibility of implementing the proposed EEMR scheme by real test data. Experimental results from industrial 4Mb memory instances show that the proposed EEMR scheme gains over 2% instance yield on average, as compared with the traditional scheme. We also investigate the reliability of the EEMR scheme with different ECC specifications and BIRA algorithms.
Keywords :
built-in self test; error correction codes; failure analysis; integrated circuit reliability; integrated memory circuits; BIRA algorithms; BISR scheme; ECC scheme; EEMR scheme; built-in redundancy-analysis algorithm; built-in self-repair scheme; embedded memories; error correction code; failure pattern sensitive; memory yield improvement scheme; realistic failure bitmaps; reliability; Algorithm design and analysis; Circuit faults; Error correction codes; Maintenance engineering; Monitoring; Redundancy; Built-In Self-Repair (BISR); Error Correction Codes (ECC); Redundancy Analysis (RA); Reliability; Yield;
Conference_Titel :
Test Conference (ITC), 2012 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4673-1594-4
DOI :
10.1109/TEST.2012.6401576