Hardware implementation of Max-Log-MAP algorithm based on MacLaurin series for turbo decoder

After the initial interest caused by appearance of turbo-codes in 1993, special attention to the hardware implementation has led to many different modified algorithms for MAP decoders. The original MAP algorithm suffers from serious drawbacks in its hardware implementation. To overcome this disadvantage, Max-Log-MAP and Log-MAP algorithms have been proposed to reduce the complexity. Recently an improved Max-Log-MAP algorithm is proposed by Shahram et. al. based on MacLaurin series to further reduce the complexity. However there are no hardware implementation reported on this particular Max-Log-MAP algorithm based on MacLaurin series. In this paper, we have proposed hardware architecture for modified Max- Log-MAP algorithm using MacLaurin series. In addition, the performance of proposed architecture is improved by replacing all the multipliers with shifters and adders. This implementation is very useful for high data rate communication applications as the performance of this decoder in lossy ISI channel is very good. Finally the performance of proposed architecture is compared with hardware implementation of Max-Log-MAP SISO decoder.