Title :
An adiabatic single phase N-type and P-type CPAL technique for full adder design
Author :
Patpatia, Bhumika ; Arora, Neha ; Singh, B.P. ; Mehta, Kavita ; Swami, Neelam
Author_Institution :
Fac. of Eng. & Technol., Mody Inst. of Technol. & Sci., Lakshmangarh, India
Abstract :
This paper presents new design techniques for adiabatic full adder cell. Adiabatic logic is the most efficient energy saving technique which provides very low power dissipation in VLSI circuits. Adiabatic Full adder is simulated by using different adiabatic techniques. Simulation results show that energy loss of adiabatic circuits can be greatly reduced by using Complementary Pass Transistor Adiabatic Logic technique. All the circuits have been simulated on BSIM3V3 90nm technology on tanner EDA tool.
Keywords :
VLSI; adders; logic design; low-power electronics; P-type CPAL technique; VLSI circuit; adiabatic full adder cell; adiabatic single phase N-type CPAL technique; complementary pass transistor adiabatic logic technique; energy loss; energy saving technique; power dissipation; tanner EDA tool; Adders; CMOS integrated circuits; Clocks; Logic gates; Power supplies; Transistors; Very large scale integration; Adiabatic Design; Full adder; Low power; Power Delay Product(PDP);
Conference_Titel :
Emerging Trends in Networks and Computer Communications (ETNCC), 2011 International Conference on
Conference_Location :
Udaipur
Print_ISBN :
978-1-4577-0239-6
DOI :
10.1109/ETNCC.2011.6255895
