Title :
An efficient hardware architecture implementing wave digital filters with reduced wordlength coefficients
Author :
Summerfield, Steve ; Wicks, Tony
Author_Institution :
Warwick Univ., Coventry, UK
Abstract :
Discusses the design and implementation of a wave digital filter architecture using coefficients that are taken from a restricted range. It outlines the possible advantages of this approach, with comparison to traditional complete coefficient ranges. Estimates of hardware speed in a VLSI implementation are made with reference to the ES2 1.5-micron process
Keywords :
VLSI; wave digital filters; 1.5 micron; VLSI implementation; hardware architecture; hardware speed; implementation; reduced wordlength coefficients; wave digital filters;
Conference_Titel :
Digital and Analogue Filters and Filtering Systems, IEE Twelfth Saraga Colloquium on
Conference_Location :
London
