Area-Efficient Processor for Public-Key Cryptography in Wireless Sensor Networks

Author

Murphy, Gerard D. ; Popovici, Emanuel M. ; Marnane, William P.

Author_Institution

Dept. of Microelectron. Eng., Univ. Coll. Cork, Cork

fYear

2008

fDate

25-31 Aug. 2008

Firstpage

667

Lastpage

672

Abstract

This paper presents a versatile public-key cryptographic processor suitable for wireless sensor networks which uses minimal hardware resources while maintaining high flexibility. The processor architecture is scalable and all hardware configurations support arbitrary bit-lengths and domain parameters. The tradeoffs between hardware area and timing for the public-key operations are demonstrated on the FPGA layer of the 25 mm Tyndall mote.

Keywords

field programmable gate arrays; public key cryptography; wireless sensor networks; FPGA layer; arbitrary bit-length; public-key cryptography processor; wireless sensor network; Arithmetic; Educational institutions; Elliptic curve cryptography; Field programmable gate arrays; Hardware; Mathematics; Public key; Public key cryptography; Radiofrequency identification; Wireless sensor networks; ECC; Low Area; Processor; RSA; Wireless Sensor Network;

fLanguage

English

Publisher

ieee

Conference_Titel

Sensor Technologies and Applications, 2008. SENSORCOMM '08. Second International Conference on

Conference_Location

Cap Esterel

Print_ISBN

978-0-7695-3330-8

Electronic_ISBN

978-0-7695-3330-8

Type

conf

DOI

10.1109/SENSORCOMM.2008.38

Filename

4622737

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2812007