Introducing OperaNP: A Reconfigurable NoC-Based Platform

In this paper, we propose a novel architecture for a reconfigurable networks on chip (NoC)-based platform called OperaNP. In this platform, intellectual property (IP) cores can be embedded on an array of programmable logic blocks while the data routing is done using another array of configurable routers. A programmable switch fabric is designed to connect the IP cores to the routers to build any desired network topology. This new design addresses the fixed topology problem in other platforms and the problem of updating the running system with new IP cores without shutting down or restarting the system. This paper introduces basic ideas behind the OperaNP project, surveys the work done in this area, and explores the art of research when designing NoC-based platform.