Ultra High Throughput Architectures for SHA-1 Hash Algorithm on FPGA

This paper first presents a new architecture of SHA-1, which achieved the theoretical upper bound on throughput in the iterative architecture. And then based on the general proposed architecture, this paper implemented other two different kinds of pipelined architectures which are based on the iterative technique and the loop unrolling technique respectively. The latter with 40-stage pipeline reached a throughput up to 76.195 Gbps on an Altera Stratix II GX EP2SGX90FF FPGA. At least to the authors´ knowledge, this is the fastest published FPGA-based design at the time of writing. At last the proposed designs are compared with other published SHA-1 designs, the designs in this paper have obvious advantages both in speed and areas.