A high-speed reconfigurable defuzzification architecture for true centre-of-gravity computations

An application specific parallel defuzzification architecture is presented which is capable of performing high-speed true centre-of-gravity (CoG) computations. This architecture uses values determined by the integrals of the output membership functions (MFs), as opposed to using singleton values. This is done by storing pre-calculated values of areas and moments within embedded memory blocks. During run-time the defuzzification processor uses these individual pre-calculated values to compute the final CoG result. The design is especially well suited for families of high capacity complex programmable logic devices (CPLDs) that have a large number of I/O pins and whose ability to be reconfigured allows the application specific pre-calculated structure to be practical for real world systems