Optimization of HV LDMOS devices accounting for packaging interaction

Author

Arienti, G. ; Imperiale, I. ; Reggiani, S. ; Gnani, E. ; Gnudi, A. ; Baccarani, G. ; Nguyen, L. ; Hernandez-Luna, A. ; Huckabee, J. ; Denison, M.

Author_Institution

DEI, Univ. of Bologna, Bologna, Italy

fYear

2015

fDate

10-14 May 2015

Firstpage

305

Lastpage

308

Abstract

The sensitivity of HV RESURF LDMOS transistors to parasitic charging in molding compound is investigated in this work by incorporating the passivation and encapsulation layers in the TCAD setup and implementing the conductivity losses in the mold. The role played by field plates and multiple metal/poly-silicon floating rings on the overall RESURF are revisited by focusing on the breakdown voltage degradation under high-voltage, high-temperature stresses. The layout re-optimization of a Single- and a Triple-RESURF LDMOS device using only MET1 and poly-Si levels is presented to reach a stable breakdown voltage after HTRB stress.

Keywords

MOSFET; encapsulation; moulding; passivation; semiconductor device breakdown; semiconductor device packaging; sensitivity analysis; HTRB stress; HV RESURF LDMOS transistor device optimization; MET1; TCAD setup; breakdown voltage degradation; conductivity losses; encapsulation layers; field plates; high-voltage high-temperature stresses; layout re-optimization; molding compound; multiple metal-poly-silicon floating rings; packaging interaction; parasitic charging; passivation; poly-silicon levels; single-RESURF LDMOS device; triple-RESURF LDMOS device; Compounds; Conductivity; Electric breakdown; Electric fields; Electric potential; Performance evaluation; Stress; LDMOS device; TCAD modeling; charge creep; packaging material;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's (ISPSD), 2015 IEEE 27th International Symposium on

Conference_Location

Hong Kong

ISSN

1943-653X

Print_ISBN

978-1-4799-6259-4

Type

conf

DOI

10.1109/ISPSD.2015.7123450

Filename

7123450