A unified ABR flow control approach for multiple-stage ingress/egress-queueing ATM switches

Most of the existing ATM available bit rate (ABR) flow control algorithms are designed based on the assumption of a simple output-buffered switch architecture. Under such an assumption, congestion can only occur at the output ports of the switch. Moreover, multiple output ports of an ATM switch can be modeled as independent queues whose congestions are independent of each other. Previously, however, research/commercial ATM switches have been evolving towards a multiple-stage architecture which contains both input and output queueing to improve capacity scalability. With the new architectures, congestion can develop at different locations within a switch. More importantly, the onset of these congestions may dependent on each other. It therefore becomes necessary for any ABR flow control algorithm to handle multiple dependent bottlenecks under such architecture. In this paper, we describe a unified ABR flow control strategy for the new generation ATM switches. Our design is geared towards the multi-stage, input/output-queueing architecture. Our strategy can be used to adapt any existing output-buffering focused, queue-length based ABR algorithm for the new architecture. As a concrete example, we discuss the adaptation of the DMRCA ABR flow control algorithm for a multiple-stage input/output queueing switch. The result is a utilization-based adaptive dual DMRCA algorithm which achieves (1) low cell-loss, (2) high switch utilization and (3) per-VC fairness in bandwidth allocation for VCs across multiple ingress buffers when traffic patterns permit. We also present results from simulation studies