Early Analysis of Timing Margins and Yield

Manufacturing process variations, leading to variability in circuit delay, can cause excessive timing yield loss if not accounted for. Many techniques have been proposed for statistical timing analysis, which operate at a late stage of the design, by which time many design decisions have already been made. In this paper, we develop an early approach to statistical timing and yield analysis. With early access to timing yield information, one can take corrective action at a time when it is still possible to do so. The proposed technique does not propagate distributions through the circuit. Instead, it provides "yield-specific" margins on the maximum and minimum nominal circuit delays (setup and hold margins) which, if applied during standard (deterministic) timing analysis, would guarantee the desired yield. Starting from a generic circuit representation based on classes of paths with different depths, we find a lower bound expression on the timing yield. This lower bound is guaranteed for unknown within-die correlations, and hence the approach can be applied pre-placement. We also propose a novel method that allows "controlled" budgeting of yield loss between setup and hold violations.