Hardware Implementation of the Salsa20 and Phelix Stream Ciphers

In this paper, we present an analysis of the digital hardware implementation of two stream ciphers proposed for the eSTREAM project: Salsa20 and Phelix. Both high speed and compact designs are examined, targeted to both field programmable (FPGA) and application specific integrated circuit (ASIC) technologies. The studied designs are specified using the VHDL hardware description language, and synthesized by using Synopsys CAD tools. The throughput of the compact ASIC design for Phelix is 260 Mbps targeted for 0.18 mu CMOS technology and the corresponding area is equivalent to about 12,400 2-input NAND gates. The throughput of Salsa20 ranges from 38 Mbps for the compact FPGA design, implemented using 194 CLB slices to 4.8 Gbps for the high speed ASIC design, implemented with an area equivalent to about 470,000 2-input NAND gates.