A digital beamforming processor for multiple beam antennas

Author

Langston, J.L. ; Hinman, K.

Author_Institution

Texas Instrum. Inc., Plano, TX, USA

fYear

1990

fDate

7-11 May 1990

Firstpage

388

Abstract

A generic digital beamformer architecture that has been implemented to demonstrate the advantages of digital beamforming is described. The digital beamforming processor has been implemented using quadratic residue number system techniques to enhance performance. The custom processor chips are implemented in 1.2- mu m CMOS technology. A digital beamformer can provide significantly better sidelobe performance than an RF beamformer. This is shown for a 64-channel system having only 8-bit weights (I and Q) and 9-bit signals (I and Q). Sidelobe levels can be suppressed 45 dB or better, Practical system implementation considerations are addressed.<>

Keywords

CMOS integrated circuits; antenna arrays; application specific integrated circuits; digital signal processing chips; 64-channel system; CMOS technology; antenna array; custom processor chips; digital beamforming processor; generic digital beamformer architecture; implementation; multiple beam antennas; quadratic residue number system techniques; Adaptive control; Apertures; Array signal processing; Directional antennas; Hardware; Integrated circuit technology; Programmable control; Radar antennas; Radar applications; Receiving antennas;

fLanguage

English

Publisher

ieee

Conference_Titel

Antennas and Propagation Society International Symposium, 1990. AP-S. Merging Technologies for the 90's. Digest.

Conference_Location

Dallas, TX, USA

Type

conf

DOI

10.1109/APS.1990.115128

Filename

115128