FPGA Implementation and Performance Evaluation of a Digital Carrier Synchronizer Using Different Numerically Controlled Oscillators

The emerging escalation in telecommunication systems has created a heightened impact on the digital integrated circuit (IC) design industry. In this day and age, Field programmable gate arrays (FPGAs) are often engaged to implement digital communication systems instead of ASICs due to the speed, performance, reliability and flexibility. Digital communication systems such as MODEM (modulation-demodulation) and M-PSK require the application of carrier synchronization in phase and frequency. Our work attains the successful FPGA implementation and emulation of a digital carrier synchronizer (DCS), which is a phase-locked loop (PLL), realized using digital circuits. The key role of this DCS depends largely on the numerically controlled oscillator (NCO). There are numerous configurations to realize NCOs that are employed in the architectural model of DCS. This paper evaluates the performance of three different NCOs realization in DCS for modem (modulator-demodulator) application using FPGA based design solutions. The configurations adopted are look up table (LUT), CORDIC and Xilinx ROM based NCO. There are advantages and trade-offs associated with each configuration. From our investigation it can be stated that the configuration of DCS involving Xilinx ROM based NCO performs better and are more suited for modem´s DCS.