DocumentCode :
2813459
Title :
Logic Design of High Density Nanomemory Using Multiple-Electron Transistors
Author :
Lee, Samuel C. ; Nguyen, Thanh X.
Author_Institution :
Univ. of Oklahoma, Norman
fYear :
2007
fDate :
22-26 April 2007
Firstpage :
1302
Lastpage :
1305
Abstract :
The purpose of this paper is to present a logic design method for representing high-density computer memory devices in nanodimensions.
Keywords :
digital storage; logic design; nanoelectronics; high density nanomemory; high-density computer memory device; logic design; multiple-electron transistor; nanodimension; Decoding; Delay; Design engineering; Helium; Hypercubes; Logic design; Multivalued logic; Nanoscale devices;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Computer Engineering, 2007. CCECE 2007. Canadian Conference on
Conference_Location :
Vancouver, BC
ISSN :
0840-7789
Print_ISBN :
1-4244-1020-7
Electronic_ISBN :
0840-7789
Type :
conf
DOI :
10.1109/CCECE.2007.331
Filename :
4232990
Link To Document :
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