A study of ESD-induced latent damage in CMOS integrated circuits

Author

Huh, Yoonjong ; Lee, Myoung G. ; Lee, Jaesik ; Jung, Hyunk C. ; Li, Tong ; Song, Du H. ; Lee, Young J. ; Hwang, Jeong M. ; Sung, Yung K. ; Kang, S.M.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

1998

fDate

March 31 1998-April 2 1998

Firstpage

279

Lastpage

283

Abstract

ESD-induced latent damage in CMOS integrated circuits has been thoroughly investigated after cumulative low-level ESD stress. A study of the latent damage for transistors at the package level has been performed with various kinds of ESD stress modes. The impact of latent damage on circuit performance degradation was also evaluated using a 64 Mb DRAM chip as a DUT.

Keywords

CMOS integrated circuits; DRAM chips; electrostatic discharge; failure analysis; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; 64 Mbit; CMOS integrated circuits; DRAM chip; ESD stress modes; ESD-induced latent damage; circuit performance degradation; cumulative low-level ESD stress; package level damage; transistor latent damage; Biological system modeling; CMOS integrated circuits; Circuit testing; Electrostatic discharge; Immune system; MOSFETs; Packaging; Stress; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 1998. 36th Annual. 1998 IEEE International

Conference_Location

Reno, NV, USA

Print_ISBN

0-7803-4400-6

Type

conf

DOI

10.1109/RELPHY.1998.670562

Filename

670562