IPC-Based Cache Partitioning: An IPC-Oriented Dynamic Shared Cache Partitioning Mechanism

In a chip-multiprocessor with a shared cache structure, the last level cache is shared by multiple applications executing simultaneously. The competing accesses from different applications degrade the system performance, resulting in non-predicting executing time. Cache partitioning techniques partition the shared cache for multiple applications. The aim of traditional cache partitioning mechanism, Utility-based Cache Partition (UCP) for example, is to lower the overall miss rate of shared cache. But the lowest miss rate doesn´t mean the highest performance (IPC). This paper investigates IPC-based Cache Partitioning (IPC-CP), an IPC performance oriented dynamic cache partitioning method. We design a Miss Rate Monitor to collect miss rate information of competing applications at run-time. Then the information collected is inputted to a Miss-Rate to IPC model to get the corresponding IPC performance. Lastly, we get the optimal cache partitioning based on IPC optimum objective function. Our evaluation, on top of a four cores CMP processor with 20 multi-programmed workloads shows that IPC-CP improves throughput by up to 53% and on average 9% over UCP.