Title :
Low-Power AES Design Using Parallel Architecture
Author :
Choi, Joong Hyun ; Choi, Hyun Suk ; Kim, Jong Tae
Author_Institution :
Sch. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon
Abstract :
This paper presents a design of AES (advanced encryption standard) with parallel architecture. The proposed architecture maintains throughput as it is but consumes lower power than the original architecture by using 1/2 clock-rate and reducing supply voltage. Models were designed using VHDL and verified by both functional and gate-level simulation. They were logically synthesized using 0.25 um, 90 nm cell library by Synopsys Design compiler. Power consumption was computed by Synopsys PrimePower.
Keywords :
cryptography; hardware description languages; low-power electronics; microprocessor chips; parallel architectures; Synopsys PrimePower; VHDL; advanced encryption standard design; cell library; functional simulatioin; gate-level simulation; parallel architecture; power consumption; Clocks; Computer architecture; Cryptography; Energy consumption; Hardware; Logic circuits; Parallel architectures; Scheduling algorithm; Throughput; Voltage; aes; low power; parallel architecture;
Conference_Titel :
Convergence and Hybrid Information Technology, 2008. ICHIT '08. International Conference on
Conference_Location :
Daejeon
Print_ISBN :
978-0-7695-3328-5
DOI :
10.1109/ICHIT.2008.191
