A High Performance VLSI Architecture for MIMO Detection in Future WLAN Receivers

Maximum likelihood (ML) detector is the optimal detector for the multiple-input multiple-output (MIMO) communication systems. Sphere decoding algorithm can achieve near optimal ML performance with reduced complexity. In this paper a new VLSI architecture for implementation of sphere decoding algorithm is proposed. The proposed architecture is fully parallel and designed based on the stack operation. The proposed architecture is implemented in 0.18 mum technology for a 4times4 QPSK MIMO system and was able to achieve a decoding throughput of 60 Mbps.