Semi-parallel reconfigurable architectures for real-time LDPC decoding

This paper presents a semi-parallel architecture for decoding low density parity check (LDPC) codes. A modified version of min-sum algorithm has been used which the advantage of simpler computations has compared to sum-product algorithm without any loss in performance. Special structure of the parity check matrix of the proposed code leads to an efficient semi-parallel implementation of the decoder for a family of (3, 6) LDPC codes. A prototype architecture has been implemented in VHDL on programmable hardware. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps.