A Novel Chaos-Based Transceiver Solution with High Data Rate Capability

In recent years, chaos-based spread spectrum systems have earned popularity due to the inherent properties of chaos signals; the primary aim of ongoing research being to develop low cost/power solutions with acceptable performance. Although systems proposed to date provide inexpensive solutions, most of the practical implementations fail to support high data-rates. The baseband chaos-based systems implemented to date have offered data-rates in the order of kbps (maximum data-rate -224 kbps). This paper presents a novel design of a chaos-based transceiver architecture with high data-rate capability based on ergodic theory of chaos. The proposed design, coded in VHDL and simulated with Quartus-II is synthesized using Altera Stratix FPGA. Post-synthesis simulation shows that the designed transceiver can be clocked at a maximum frequency of 180.12 MHz, thus, supporting data rates of about 15.01 Mbps. Power consumption of complete transceiver is about 1.284 W, with a power efficiency of 7.704 mW/MS/s.