A study of slipstream processors

A slipstream processor reduces the length of a running program by dynamically skipping computation non-essential for correct forward progress. The shortened program runs faster as a result, but it is speculative. So a second unreduced copy of the program is run concurrently with and slightly behind the reduced copy-leveraging a chip multiprocessor (CMP) or simultaneous multithreading (SMT). The short program passes its control and data flow outcomes to the fill program for checking. And as it checks the short program, the full program fetches and executes more efficiently, due to having an accurate picture of the future. Both programs are sped up: combined, they outperform conventional non-redundant execution. We study slipstreaming with the following key results. 1. A 12% average performance improvement is achieved by harnessing an otherwise unused, additional processor in a CMP. Slipstreaming using two small superscalar cores often achieves similar instructions-per-cycle as one large superscalar core, bur with a potentially faster clock and a more flexible architecture. 2. A majority of the benchmarks show significant reduction in the short program (about 50%). Slipstreaming using an 8-way SMT processor improves their performance from 10% to 20%. 3. For some benchmarks, including gcc, performance improvement is due to the short program resolving branch mispredictions in advance. Others benefit largely due to value predictions from the short program, and the effect is not always reproducible by conventional value prediction tables. 4. As execution bandwidth is increased, slipstreaming provides less of a performance advantage-unless instructions are removed in the short program before they are fetched. A simple program sequencing mechanism is developed to bypass instruction fetching