Low-Voltage Single-Phase Clocked Quasi-Adiabatic Pass-Gate Logic

Energy recovering circuitry based on adiabatic principles is a new technique leading towards low-power circuit design. The ability to recover energy dissipated while the circuit´s capacitive nodes are discharged is an attractive feature in mobile electronic applications which will increase battery life, especially for SoC´s fabricated in submicron CMOS processes. In this paper, we propose a novel low-voltage Quasi-Adiabatic Pass-Gate Logic (QAPG) family using a single power clock in 90 nm CMOS technology. We perform a comparative analysis in which cells are constructed using previously proposed low power single-phase clocked adiabatic logic and our newly proposed QAPG logic for the implementation of a full adder. Simulations demonstrate that the new logic family is suitable for low voltage operation down to 0.26V with low voltage operational frequencies up to 250 MHz. In addition, QAPG is six to twenty times more energy efficient than previously proposed adiabatic logic at low-voltages.