A Flow for Self-Reconfigurable Embedded Architectures and Co-Design Environments

This paper discusses the novel idea of testing digital circuits using run-time reconfigurable techniques, in order to minimize circuit area, as well as test generation and application time. The idea revolves around the dynamic partial reconfiguration of circuits under test, in order to inject stuck-at faults at different locations of the circuit, and uncover both detectable and undetectable faults. The paper presents a practical implementation of run-time reconfigurable methodologies using an actual reconfigurable device, the Xilinx Virtex-II, in the development of a test architecture.