High-performance asic architecture for hysteresis thresholding and component feature extraction in limited-resource applications

Hysteresis thresholding offers enhanced object detection but is time-consuming. Hence, it is often avoided in real-time, constrained streaming processors. We propose a high-performance solution for limited-resource applications. This features two memory-efficient and fast architectures for hysteresis thresholding followed by object feature extraction: a lower-area uniform implementation and a faster pipelined one with slight area increase. Both designs couple thresholding with candidate pixel handling, component analysis, and feature extraction on the fly. This avoids multiple scans of the image, additional label resolving, and large image buffers; thus offering an average speedup up to 37× with about 99% memory reduction compared to state of the art schemes for VGA images. Moreover, the ASIC implementation allows this process to be done at 460fps, making the integration of this part into real-time detection systems very feasible.