Abstract :
A national project on a superconducting system design is outlined. The project was launched in 1981 and finished in January, 1990. The basic concept of system construction is called PHI, standing for the following key technologies: parallel processing for high-speed computing, hierarchical memory for high-speed and large-capacity storage, and user-friendly interface. The objective performances for logic LSIs were set at 30 ps/gate at room temperature and 10 ps/gate at 77 K. For the memory LSIs, faster address access time than 10 ns with 16 kbit complexity was targeted. Josephson junction device, GaAs MESFET, and HEMT technologies were developed to achieve the above performance goals. For overall evaluation of basic technologies, two parallel processing systems were built. The first one, using 3 MESFETs and 4 HEMTs, operates at more than 10-GFLOPS with 4 processors. The other system implementing 2 MESFETs and 1 HEMT, shows a special capacity for ultra-high-speed data processing in satellite communication systems.<>
Keywords :
III-V semiconductors; field effect integrated circuits; gallium arsenide; integrated logic circuits; integrated memory circuits; large scale integration; random-access storage; superconducting logic circuits; superconducting memory circuits; 10 GFLOPS; 10 ps; 16 kbit; 30 ps; 300 K; 77 K; GaAs; HEMT; Japanese national project; Josephson junction device; MESFET; PHI; address access time; device technologies; hierarchical memory; high speed storage; high-speed computing; large-capacity storage; logic LSIs; memory LSIs; objective performances; parallel processing; room temperature operation; satellite communication systems; super computer system; superconducting system design; ultra-high-speed data processing; user-friendly interface; Computer interfaces; Concurrent computing; Gallium arsenide; HEMTs; Josephson junctions; Logic devices; MESFETs; Parallel processing; Superconducting logic circuits; Temperature;
