A high-speed GaAs 16 Kb SRAM of 4.4 ns/2 W using triple-level metal interconnection

Author

Nakano, Hirofumi ; Noda, Minoru ; Sakai, Masapki ; Matsue, Shuichi ; Oku, Tomoki ; Sumitani, Kouichi ; Makino, Hiroshi ; Takano, Hirozo ; Nishitani, Kazuo

Author_Institution

Mitsubishi Electric Corp., Hyogo, Japan

fYear

1990

fDate

7-10 Oct. 1990

Firstpage

151

Lastpage

154

Abstract

A fully functional GaAs 16 K SRAM is realized with an address access time of 4.4 ns and a power dissipation of 2 W. In the fabrication process, a triple-level Au-based interconnection technology is developed to reduce the wiring length, which strongly affects the delay time. The wiring length and chip size are drastically reduced to 69% and 58% of those previously reported by the authors, respectively. High wafer yield of 10% is also obtained by using this technology. Moreover, high-speed and stable operation of less than 5 ns is achieved for the temperature range from 25 to 100 degrees C.<>

Keywords

III-V semiconductors; SRAM chips; gallium arsenide; integrated circuit technology; metallisation; 2 W; 25 to 100 degC; 4.4 ns; Au; GaAs; address access time; chip size; delay time; power dissipation; stable operation; triple-level metal interconnection; wafer yield; wiring length; Etching; Gallium arsenide; Large scale integration; Microwave devices; Planarization; Power dissipation; Random access memory; Shape; Temperature; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1990. Technical Digest 1990., 12th Annual

Conference_Location

New Orleans, LA, USA

Type

conf

DOI

10.1109/GAAS.1990.175473

Filename

175473