A multi-chip packaged GaAs 16*16 bit parallel multiplier

Author

Sekiguchi, T. ; Sawada, S. ; Hirose, T. ; Nishiguchi, M. ; Shiga, N. ; Hayashi, H.

Author_Institution

Sumitomo Electric Ind. Ltd., Sakae-ku, Yokohama, Japan

fYear

1990

fDate

7-10 Oct. 1990

Firstpage

199

Lastpage

202

Abstract

A GaAs 16*16 16-bit parallel multiplier utilizing multichip packaging technology is demonstrated. This multichip approach was taken in an effort to realize GaAs ULSIs with high yield and reliability, using multiple smaller scale integrated circuits. The device is composed of four GaAs 8*8-bit expandable parallel multipliers and a multichip package (MCP). The developed 8*8 multipliers consist of 1097 enhancement/depletion DCFL (directly coupled FET logic) gates each, and have a 3.4 ns multiplication time. The developed MCP is composed of five layers of alumina ceramic which include 50 Omega striplines. The multiplication time of this 16*16-bit multichip multiplier is 7.6 ns, and the total production yield is 70%.<>

Keywords

III-V semiconductors; VLSI; field effect integrated circuits; gallium arsenide; multiplying circuits; 3.4 ns; DCFL; ULSIs; expandable parallel multipliers; multichip package; multichip packaging technology; multiplication time; parallel multiplier; production yield; reliability; yield; Coupling circuits; FETs; Gallium arsenide; Integrated circuit packaging; Integrated circuit reliability; Integrated circuit technology; Integrated circuit yield; Logic devices; Logic gates; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1990. Technical Digest 1990., 12th Annual

Conference_Location

New Orleans, LA, USA

Type

conf

DOI

10.1109/GAAS.1990.175486

Filename

175486