Title :
GaAs MESFET LSI design using E/D-DCFL circuits
Author :
Onodera, T. ; Onodera, H. ; Sugisaki, S. ; Okamoto, M. ; Suyama, K. ; Kuryu, I. ; Nishi, H.
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
Abstract :
GaAs MESFET LSI design using E/D-DCFL (enhancement/depletion-directly coupled FET logic) circuits is considered. Monte Carlo DC SPICE simulation is used to assess the effect of the FET parameter spread on the functional yield of a chip. It is found that the important factors for obtaining a high functional yield are strict control of the FET characteristics and the stability and uniformity of the supply voltage on the chip. The functional yield model, including the supply voltage drop, agrees well with the results obtained in experiments on a 5 K gate array IC fabricated with 0.8- mu m-gate BP-MESFETs.<>
Keywords :
III-V semiconductors; Monte Carlo methods; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated logic circuits; large scale integration; logic design; 0.8 micron; E/D-DCFL circuits; FET parameter spread; GaAs; MESFET LSI design; Monte Carlo DC SPICE simulation; directly coupled FET logic; enhancement/depletion; functional yield model; gate array IC; stability; supply voltage; Coupling circuits; FETs; Gallium arsenide; Integrated circuit modeling; Large scale integration; Logic circuits; Logic design; MESFET circuits; Monte Carlo methods; SPICE;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1990. Technical Digest 1990., 12th Annual
Conference_Location :
New Orleans, LA, USA
DOI :
10.1109/GAAS.1990.175491
