Title :
Design and simulation analysis of UART IP Core
Author_Institution :
Comput. Applic. Dept., Chongqing Coll. of Electron. Eng., Chongqing, China
Abstract :
Based on mastering SOPC and Quartus II, designed UART IP Core, and an integrity design proposal is given out. The proposal is embedded in FPGA chip. The transmitter module, receiver module and baud rate generator are simulated and analyses. The experiments results show that the design method is compact and practical, and the circuit is stable, reliable, and strong flexibility.
Keywords :
computer interfaces; data communication equipment; embedded systems; field programmable gate arrays; industrial property; integrated circuit design; system-on-chip; FPGA chip; Quartus II; SOPC; UART IP core; baud rate generator; integrity design proposal; Field programmable gate arrays; IEC standards; IP networks; Industrial control; Integrated circuit reliability; Presses; Proposals; ModelSim; SOPC; UART IP Core;
Conference_Titel :
Mechanic Automation and Control Engineering (MACE), 2011 Second International Conference on
Conference_Location :
Hohhot
Print_ISBN :
978-1-4244-9436-1
DOI :
10.1109/MACE.2011.5988319
