Non-iterative high speed division computation based on Mitchell logarithmic method

A novel non-iterative circuit for computing division based on logarithm is proposed in the paper. Mitchell-based methods are used for the logarithmic and antilogarithmic conversions. Merging the conversion stages in the implementation is not possible if the existing antilogarithmic conversion algorithms are used. Thus, the critical path has at least two carry propagate adders (CPAs). This work introduces a new antilogarithmic algorithm to merge the two conversion stages into a single one to remove one of the two CPAs. Compared to the best existing Mitchell-based logarithmic division computation method used in a 3-D graphic system, the proposed design achieves improvements by 45.4% and 34.8%, respectively, in computation speed and area-delay product with an area overhead of 19.5%.