A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS

Author

Wen-Lan Wu ; Yan Zhu ; Li Ding ; Chi-Hang Chan ; U-Fat Chio ; Sai-Weng Sin ; Seng-Pan, U. ; Martins, Rui P.

Author_Institution

State-Kay Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China

fYear

2013

fDate

19-23 May 2013

Firstpage

2239

Lastpage

2242

Abstract

This paper presents a monotonic multi-switching technique that is implemented in a 8b SAR ADC. The proposed switching reduces 1/2 total DAC capacitance and achieves more than 80% switching energy saving when compared to the most advanced V_CM-based or merged capacitor switching methods. Besides, conversion redundancies are added to compensate the errors resulting from insufficient DAC settling and reference noise. The proposed 8-bit SAR ADC operates at 100MS/s with 0.6V supply in 65nm CMOS. The simulation results show that the design achieves 48.8dB SNDR with only 0.524mW power. The Figure-of-Merit (FoM) is 23.35fJ/conversion-step.

Keywords

CMOS integrated circuits; analogue-digital conversion; capacitance; digital-analogue conversion; redundancy; CMOS; DAC capacitance; FoM; SAR ADC; SNDR; capacitor switching methods; figure-of-merit; monotonic multiswitching technique; power 0.524 mW; size 65 nm; storage capacity 8 bit; switching energy saving; voltage 0.6 V; Arrays; Capacitance; Capacitors; Redundancy; Resistance; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6572322

Filename

6572322